library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
--top_begin
entity top is
	Port(
		clk		: in std_logic; --clk
		enable	: in std_logic;
		reset	: in std_logic;
		
		--begin FFT512 ports
		in_top_im512 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      in_top_re512 : in STD_LOGIC_VECTOR ( 7 downto 0 );		
		out_top_im512 : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      out_top_re512 : out STD_LOGIC_VECTOR ( 7 downto 0 )	;	
    	
	--	end FFT512 ports
	
	--begin FFT256 ports
		in_top_im256 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      in_top_re256 : in STD_LOGIC_VECTOR ( 7 downto 0 );		
		out_top_im256 : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      out_top_re256 : out STD_LOGIC_VECTOR ( 7 downto 0 )	;	
    	
	--	end FFT256 ports
	
	
	--begin FFT128 ports
		in_top_im128 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
      in_top_re128 : in STD_LOGIC_VECTOR ( 7 downto 0 );		
		out_top_im128 : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      out_top_re128 : out STD_LOGIC_VECTOR ( 7 downto 0 )		
    	
	--	end FFT128 ports
		
		);
end top;
--top_end
architecture Behavioral of top is

-----------------------------------------------------
component static is
	Port(
		clk			: in std_logic;
		reset			: in std_logic;
		--begin FFT512 ports
		static_in_im512		: in std_logic_vector(7 downto 0);
		static_in_re512	   : in std_logic_vector(7 downto 0);
		static_out_im512		: out std_logic_vector(7 downto 0);
		static_out_re512	   : out std_logic_vector(7 downto 0);
		--end FFT512 ports
		
		--begin FFT256 ports
		static_in_im256		: in std_logic_vector(7 downto 0);
		static_in_re256	   : in std_logic_vector(7 downto 0);
		static_out_im256		: out std_logic_vector(7 downto 0);
		static_out_re256	   : out std_logic_vector(7 downto 0);
		--end FFT256 ports
		
		--begin FFT128 ports
		static_in_im128		: in std_logic_vector(7 downto 0);
		static_in_re128	   : in std_logic_vector(7 downto 0);
		static_out_im128		: out std_logic_vector(7 downto 0);
		static_out_re128	   : out std_logic_vector(7 downto 0)
		--end FFT128 ports
		
		);
end component;
attribute box_type : string;
attribute box_type of static : component is "black_box";


-----------------------------------------------------
component FFT_Wrapper is
	Port(
	 
	 xn_re : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    xk_im : out STD_LOGIC_VECTOR (7 downto 0 ); 
    xk_re : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    xn_im : in STD_LOGIC_VECTOR ( 7 downto 0 );
	 clk: IN std_logic);


end component;


component FFT_Wrapper256 is
	Port(
	 
	 xn_re : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    xk_im : out STD_LOGIC_VECTOR (7 downto 0 ); 
    xk_re : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    xn_im : in STD_LOGIC_VECTOR ( 7 downto 0 );
	 clk: IN std_logic);


end component;

component FFT_Wrapper128 is
	Port(
	 
	 xn_re : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    xk_im : out STD_LOGIC_VECTOR (7 downto 0 ); 
    xk_re : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    xn_im : in STD_LOGIC_VECTOR ( 7 downto 0 );
	 clk: IN std_logic);


end component;




signal xn_im_s512:std_logic_vector(7 downto 0);
signal xn_re_s512:std_logic_vector(7 downto 0);

signal xn_im_s256:std_logic_vector(7 downto 0);
signal xn_re_s256:std_logic_vector(7 downto 0);

signal xn_im_s128:std_logic_vector(7 downto 0);
signal xn_re_s128:std_logic_vector(7 downto 0);

--------------------------------------------------
begin

------PRR_begin ::FFT_Wrapper :: FFT
FFT : FFT_Wrapper
	Port Map(
		
		xn_re	=> xn_re_s512,
		xk_im => out_top_im512,
		xk_re	=> out_top_re512,
		xn_im	=> xn_im_s512,
		clk		=> clk
		);
------PRR_end

------PRR_begin ::FFT_Wrapper256 :: FFT256
FFT256 : FFT_Wrapper256
	Port Map(
		
		xn_re	=> xn_re_s256,
		xk_im => out_top_im256,
		xk_re	=> out_top_re256,
		xn_im	=> xn_im_s256,
		clk		=> clk
		);
------PRR_end

------PRR_begin ::FFT_Wrapper128 :: FFT128
FFT128 : FFT_Wrapper128
	Port Map(
		
		xn_re	=> xn_re_s128,
		xk_im => out_top_im128,
		xk_re	=> out_top_re128,
		xn_im	=> xn_im_s128,
		clk		=> clk
		);
------PRR_end






--static_begin :: static
StaticA : static
	Port Map(
		clk					=> clk,
		reset					=> reset,
		
		static_in_im512	=> in_top_im512,
		static_in_re512	=> in_top_re512,
		static_out_im512	=> xn_im_s512,
		static_out_re512	=> xn_re_s512,
		
		static_in_im256	=> in_top_im256,
		static_in_re256	=> in_top_re256,
		static_out_im256	=> xn_im_s256,
		static_out_re256	=> xn_re_s256,
		
		static_in_im128	=> in_top_im128,
		static_in_re128	=> in_top_re128,
		static_out_im128	=> xn_im_s128,
		static_out_re128	=> xn_re_s128
		
		);
--static_end
-------------------------------------------------------

end Behavioral;
